The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2008

Filed:

Nov. 21, 2005
Applicant:

Michael L. Lovejoy, Albuquerque, NM (US);

Inventor:

Michael L. Lovejoy, Albuquerque, NM (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write address count, while a read address counter stores a read address count. Finally, a backup circuit receives a read address associated with data read from a slot of the plurality of slots. According to an alternate embodiment, a most significant bit circuit is coupled to an output of the write address counter for setting the most significant bit of the write address. A method of reading data stored in an asynchronous FIFO memory of an integrated circuit is also disclosed.


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Lovejoy, Michael. (2008). Circuit for and method of reading data in an asynchronous fifo including a backup address circuit for re-reading data (U.S. Patent No. 7436726). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7436726

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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