The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7435352 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 14, 2008

Filed:

Oct. 02, 2003
Applicants:

Jee-soo Mok, Chungcheongbuk-do, KR;

Jang-kyu Kang, Daejeon, KR;

Chang-hyun Nam, Chungcheongbuk-do, KR;

Inventors:

Jee-Soo Mok, Chungcheongbuk-do, KR;

Jang-Kyu Kang, Daejeon, KR;

Chang-Hyun Nam, Chungcheongbuk-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01B 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a solder resist pattern includes laminating a semi-cured thermosetting film on both sides of a substrate and laser ablating the laminated thermosetting film according to a solder resist mask pattern. The method is applicable to multilayer printed circuit boards, which are fabricated either by the buildup process or the parallel process. Lower manufacturing costs and improved accuracy of the solder resist pattern can be achieved due to the simplified process.


Find Patent Forward Citations

Mok, Jee-Soo. (2008). Method of forming solder resist pattern (U.S. Patent No. 7435352). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7435352

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…