The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2008

Filed:

Jun. 23, 2006
Applicants:

Hirobumi Inoue, Tokyo, JP;

Daisuke Ohshima, Tokyo, JP;

Jun Sakai, Tokyo, JP;

Mitsuru Furuya, Tokyo, JP;

Inventors:

Hirobumi Inoue, Tokyo, JP;

Daisuke Ohshima, Tokyo, JP;

Jun Sakai, Tokyo, JP;

Mitsuru Furuya, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.


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