The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Aug. 05, 2005
Applicants:
Cyrus Chu, Fremont, CA (US);
Wen Yi Huang, Donggang Township, Pingtung County, TW;
Inventors:
Cyrus Chu, Fremont, CA (US);
Wen Yi Huang, Donggang Township, Pingtung County, TW;
Assignee:
Terawins, Inc., Zhong-He, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 9/455 (2006.01); H04N 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.