The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Jul. 31, 2006
Weiwei Mao, Macungie, PA (US);
Weiwei Mao, Macungie, PA (US);
Agere Systems, Inc., Allentown, PA (US);
Abstract
A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.