The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2008

Filed:

May. 05, 2006
Applicants:

Ira G. Miller, Tempe, AZ (US);

Eduardo Velarde, Chandler, AZ (US);

Inventors:

Ira G. Miller, Tempe, AZ (US);

Eduardo Velarde, Chandler, AZ (US);

Assignee:

Micrel, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/62 (2006.01); G05F 1/595 (2006.01); G05F 3/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PWM regulator is operated either a buck mode or a boost mode depending on whether the input voltage is above or below the desired regulated output voltage. The technique uses two sawtooth ramps 180 degrees out of phase. Where the two ramps cross each other is a buck/boost transition level. An error voltage, corresponding to a required duty cycle to achieve a regulated voltage, is compared to the two ramps. The transition from one mode to the other occurs when the error voltage passes the buck/boost transition level of the two ramps. A logic circuit supplies PWM pulses to either buck switching transistors or the boost switching transistors in a power stage of the regulator, depending on the whether the error voltage is above or below the buck/boost transition level, to achieve the regulated voltage.


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