The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Sep. 28, 2004
Hon Kin Chiu, Hayward, CA (US);
Hon Kin Chiu, Hayward, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A level-shifting inverting circuit provides a blanking signal to Gridof a CRT. The circuit provides the blanking signal from a blanking logic signal according to a voltage transfer characteristic that is substantially similar to the voltage transfer characteristic of a standard CMOS inverter. Also, the level-shifting inverting circuit includes a switch circuit that includes a differential pair. The differential pair has the blanking logic signal at one input, and a bias signal at the other input. The switch circuit is coupled to a voltage divider that provides an output voltage that is pre-determined by a resistor ratio when the switch circuit is open. If the blanking logic signal is low, the switch circuit is open. Conversely, if the blanking logic signal is high, the switch circuit is closed, and sinks current from the voltage divider, causing the output voltage to correspond to a second pre-determined voltage level.