The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2008

Filed:

Dec. 27, 2006
Applicants:

Sung-tae Lee, Suwon-si, KR;

Sun-young Kim, Yongin-si, KR;

Young-soo Song, Incheon, KR;

Inventors:

Sung-Tae Lee, Suwon-si, KR;

Sun-Young Kim, Yongin-si, KR;

Young-Soo Song, Incheon, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a method for fabricating a semiconductor device having reduced contact resistance. In the method, gate patterns defining a narrow opening and a wide opening are formed having an upper portion of a predetermined region of a semiconductor substrate. After gate spacers are formed on sidewalls of the gate patterns, an ion implantation process that uses the gate patterns and the gate spacers as an ion mask is performed to form a plug doped region in a portion of the semiconductor substrate that is located below the wide opening. At this point, the gate spacers are formed to expose a portion of a bottom surface of the wide opening and to fill a lower portion of the narrow opening.


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