The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2008

Filed:

Nov. 17, 2005
Applicants:

Lin-shih Liu, Fremont, CA (US);

Mark T. Chan, San Jose, CA (US);

Inventors:

Lin-Shih Liu, Fremont, CA (US);

Mark T. Chan, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.


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