Clock signal generating circuit, semiconductor integrated circuit and method for controlling a frequency division ratio

Abstract

A clock signal generating circuit is disclosed. The clock signal generating circuit includes: a reference clock signal generating unit for generating a reference clock signal; a plurality of frequency dividing units for carrying out frequency dividing of the reference clock signal and outputting frequency-divided clock signals; a plurality of frequency division ratio storing units for storing frequency division ratios different from each other for the respective frequency dividing units; and a switching unit for switching, synchronously with the reference clock signal, at least one initial frequency division ratio at the frequency dividing units to the frequency division ratios stored in the corresponding frequency division ratio storing units.