The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2008

Filed:

Dec. 21, 2006
Applicants:

Chul Young Ham, Guri-si, KR;

Noh Yeal Kwak, Icheon-si, KR;

Inventors:

Chul Young Ham, Guri-si, KR;

Noh Yeal Kwak, Icheon-si, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.


Find Patent Forward Citations

Ham, Chul. (2008). Method of forming isolation layer of semiconductor device (U.S. Patent No. 7429519). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7429519

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…