The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2008
Filed:
Feb. 13, 2004
Michiel Jos Van Duuren, Leuven, BE;
Robertus Theodorus Fransiscus Van Schaijk, Leuven, BE;
Youri Ponomarev, Leuven, BE;
Jacob Christopher Hooker, Leuven, BE;
Michiel Jos Van Duuren, Leuven, BE;
Robertus Theodorus Fransiscus Van Schaijk, Leuven, BE;
Youri Ponomarev, Leuven, BE;
Jacob Christopher Hooker, Leuven, BE;
NXP B.V., Eindhoven, NL;
Abstract
In the method for manufacturing a semiconductor device (), which comprises a semiconducting body () having a surface () with a source region () and a drain region () defining a channel direction () and a channel region (), a first stack () of layers on top of the channel region (), the first stack () comprising, in this order, a tunnel dielectric layer (), a charge storage layer () for storing an electric charge and a control gate layer (), and a second stack () of layers on top of the channel region () directly adjacent to the first stack () in the channel direction (), the second stack () comprising an access gate layer () electrically insulated from the semiconducting body () and from the first stack (), initially a first sacrificial layer () is used, which is later replaced by the control gate layer (). A second sacrificial layer () is used to protect the part () off the surface () adjacent to the second sidewall () and opposite to the position () of the second stack () when providing the access gate layer ().