The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2008
Filed:
Mar. 15, 2005
Sung-min Kim, Incheon-si, KR;
Kyoung-hwan Yeo, Seoul, KR;
In-soo Jung, Gyeonggi-do, KR;
Si-young Choi, Gyeonggi-do, KR;
Dong-won Kim, Gyeonggi-do, KR;
Yong-hoon Son, Gyeonggi-do, KR;
Young-eun Lee, Gyeonggi-do, KR;
Byeong-chan Lee, Gyeonggi-do, KR;
Jong-wook Lee, Gyeonggi-do, KR;
Sung-Min Kim, Incheon-si, KR;
Kyoung-Hwan Yeo, Seoul, KR;
In-Soo Jung, Gyeonggi-do, KR;
Si-Young Choi, Gyeonggi-do, KR;
Dong-Won Kim, Gyeonggi-do, KR;
Yong-Hoon Son, Gyeonggi-do, KR;
Young-Eun Lee, Gyeonggi-do, KR;
Byeong-Chan Lee, Gyeonggi-do, KR;
Jong-Wook Lee, Gyeonggi-do, KR;
Abstract
Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.