The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2008
Filed:
Oct. 08, 2007
Vance D. Archer, Iii, Greensboro, NC (US);
Kouros Azimi, Center Valley, PA (US);
Daniel Patrick Chesire, Winter Garden, FL (US);
Warren K Gladden, Macungie, PA (US);
Seung H. Kang, Sinking Spring, PA (US);
Taeho Kook, Orlando, FL (US);
Sailesh M. Merchant, Macungie, PA (US);
Vivian Ryan, Hampton, NJ (US);
Vance D. Archer, III, Greensboro, NC (US);
Kouros Azimi, Center Valley, PA (US);
Daniel Patrick Chesire, Winter Garden, FL (US);
Warren K Gladden, Macungie, PA (US);
Seung H. Kang, Sinking Spring, PA (US);
Taeho Kook, Orlando, FL (US);
Sailesh M. Merchant, Macungie, PA (US);
Vivian Ryan, Hampton, NJ (US);
Agere Systems, Inc., Allentown, PA (US);
Abstract
An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.