The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2008
Filed:
Jul. 16, 2004
Michael J. Schulte, Madison, WI (US);
Erdem Hokenek, Yorktown Heights, NY (US);
Pablo I. Balzola, Nanuet, NY (US);
C. John Glossner, Carmel, NY (US);
Michael J. Schulte, Madison, WI (US);
Erdem Hokenek, Yorktown Heights, NY (US);
Pablo I. Balzola, Nanuet, NY (US);
C. John Glossner, Carmel, NY (US);
Sandbridge Technologies, Inc., White Plains, NY (US);
Abstract
An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithmetic unit comprises first arithmetic circuitry, second arithmetic circuitry, selection circuitry and saturation circuitry. The first arithmetic circuitry, which may comprise a carry-propagate adder, processes the first portions of the input operands to generate at least a temporary sum and a carry output. The second arithmetic circuitry, which may comprise a dual adder and a preliminary saturation detector, processes the second portions of the input operands to generate one or more temporary sums and a number of saturation flags. The selection circuitry is configured to select one or more of the outputs of the second arithmetic circuitry based on the carry output of the first arithmetic circuitry. The saturation circuitry has inputs coupled to corresponding outputs of the first arithmetic circuitry and the selection circuitry, and is configured to generate a result of the arithmetic operation.