The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2008
Filed:
Oct. 03, 2006
Applicant:
Chi Fung Cheng, San Jose, CA (US);
Inventor:
Chi Fung Cheng, San Jose, CA (US);
Assignee:
Marvell International Ltd., Hamilton, BM;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/16 (2006.01);
U.S. Cl.
CPC ...
Abstract
A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.
Cheng, Chi. (2008). High bandwidth phase locked pool (pll) (U.S. Patent No. 7427883). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7427883
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile