The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2008
Filed:
Aug. 05, 2005
Applicant:
Satish R. Ganesan, Mountain View, CA (US);
Inventor:
Satish R. Ganesan, Mountain View, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/00 (2006.01); G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
Abstract
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bus should be used. In one embodiment, a latency constraint is used to determine whether a lower latency design with arbitration logic at the slave modules is to be used. In one embodiment, throughput constraints are used to determine whether a higher throughput design with arbitration logic at the slave modules is to be used.