All-digital phase-locked loop for a digital pulse-width modulator

Abstract

A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.