The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2008
Filed:
Feb. 09, 2005
Pierangelo Confalonieri, Caponago, IT;
Marco Zamprogno, Cesano Maderno, IT;
Federico Garibaldi, Arcore, IT;
Pierangelo Confalonieri, Caponago, IT;
Marco Zamprogno, Cesano Maderno, IT;
Federico Garibaldi, Arcore, IT;
STMicroelectronics S.r.l., Agrate Brianza, IT;
Abstract
A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.