The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Mar. 23, 2004
Applicants:
Parag P Mehta, Ladera Ranch, CA (US);
Patrick J. Kennedy, Mission Viejo, CA (US);
Inventors:
Parag P Mehta, Ladera Ranch, CA (US);
Patrick J. Kennedy, Mission Viejo, CA (US);
Assignee:
QLOGIC, Corporation, Aliso Viejo, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A PCI-Express slot for coupling devices to a host system is provided. The slot includes a PCI-Express connector that can couple at least two devices using at least two independent PCI-Express lanes. Four, eight, twelve, sixteen, and/or thirty PCI-Express lanes are used to couple at least two devices, and/or eight PCI-Express lanes are used to couple at least two devices.
Mehta, Parag. (2008). Pci—express slot for coupling plural devices to a host system (U.S. Patent No. 7424564). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7424564
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile