System and method for clock domain grouping using data path relationships

Abstract

A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.