Phase error detecting circuit and synchronization clock extraction circuit

Abstract

In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generatorinputs, as a rising cross reference value S, rising phase error data Scalculated in a phase error calculatorto a rising cross detectorand inputs, as a falling cross reference value S, falling phase error data Ssimilarly calculated to a falling cross detector. Each of the cross detectorsandcalculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) Sor Sand outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.