The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Jan. 30, 2007
Applicants:
Alain Vergnes, Trets, FR;
Eric Matulik, Meyreuil, FR;
Frederic Schumacher, aix en Provence, FR;
Inventors:
Assignee:
Atmel Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2X clock signal.