The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7423472 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 09, 2008

Filed:

Mar. 28, 2006
Applicants:

Masaya Hirose, Kyoto, JP;

Kinya Daio, Kyoto, JP;

Masahiro Gion, Kyoto, JP;

Masato Maede, Osaka, JP;

Hisaki Watanabe, Osaka, JP;

Inventors:

Masaya Hirose, Kyoto, JP;

Kinya Daio, Kyoto, JP;

Masahiro Gion, Kyoto, JP;

Masato Maede, Osaka, JP;

Hisaki Watanabe, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuithas a control signal terminal INCNT, a first power imputer terminal IG, and a second power supply terminal IGas input terminals and has a first output terminal OGand a second output terminal OGas output terminals. The gate of a second P-type transistor Pis connected to the first output terminal OGof the gate control circuitand the gate of a second P-type transistor Pis connected to the second output terminal OGof the gate control circuit, wherein the first P-type transistor Pand the second P-type transistor Pare connected in series between a first power source VDDand a second power source VDDto form a switch section.


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