logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7423324 B1

PDFFull Text
Date of Patent:
Sep. 09, 2008

Filed:

Apr. 05, 2005

Double-gate mos transistor, double-gate cmos transistor, and method for manufacturing the same

Applicants:

Toshihiro Sekigawa, Ibaraki, JP;

Yongxun Liu, Ibaraki, JP;

Meishoku Masahara, Ibaraki, JP;

Hanpei Koike, Ibaraki, JP;

Eiichi Suzuki, Ibaraki, JP;

Inventors:

Toshihiro Sekigawa, Ibaraki, JP;

Yongxun Liu, Ibaraki, JP;

Meishoku Masahara, Ibaraki, JP;

Hanpei Koike, Ibaraki, JP;

Eiichi Suzuki, Ibaraki, JP;

Assignee:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Attorney:

Rader, Fishman & Grauer, PLLC

Primary Examiner:

Ida M Soward

Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 29/00 (2006.01); H01L 27/10 (2006.01); H01L 29/739 (2006.01); H01L 29/73 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 31/062 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.

Find Patent Forward Citations

Loading…