The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
May. 10, 2004
R. Stephen Polzin, San Jose, CA (US);
Frederick D. Weber, San Jose, CA (US);
Gerald R. Talbot, Concord, MA (US);
Larry D. Hewitt, Austin, TX (US);
Richard W. Reeves, Westboro, MA (US);
Shwetal A. Patel, San Jose, CA (US);
Ross V. LA Fetra, Sunnyvale, CA (US);
Dale E. Gulick, Austin, TX (US);
Mark D. Hummel, Franklin, MA (US);
Paul C. Miranda, Austin, TX (US);
R. Stephen Polzin, San Jose, CA (US);
Frederick D. Weber, San Jose, CA (US);
Gerald R. Talbot, Concord, MA (US);
Larry D. Hewitt, Austin, TX (US);
Richard W. Reeves, Westboro, MA (US);
Shwetal A. Patel, San Jose, CA (US);
Ross V. La Fetra, Sunnyvale, CA (US);
Dale E. Gulick, Austin, TX (US);
Mark D. Hummel, Franklin, MA (US);
Paul C. Miranda, Austin, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.