The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2008

Filed:

Aug. 24, 2005
Applicants:

Michael G. Ahrens, Sunnyvale, CA (US);

Shahin Toutounchi, Pleasanton, CA (US);

James Karp, Saratoga, CA (US);

Jongheon Jeong, Palo Alto, CA (US);

Inventors:

Michael G. Ahrens, Sunnyvale, CA (US);

Shahin Toutounchi, Pleasanton, CA (US);

James Karp, Saratoga, CA (US);

Jongheon Jeong, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.


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