The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7420489 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 02, 2008

Filed:

Apr. 21, 2006
Applicant:

Hitoshi Watanabe, Shinjuku-ku, JP;

Inventor:

Hitoshi Watanabe, Shinjuku-ku, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A verifying method and apparatus verifies operation of a semiconductor circuit device by inputting, to a logical simulator, logical models representing a logic circuit and an analog circuit, adding, to the logical model representing the analog circuit, a function that generates a function value in accordance with the state of connections between terminals of the analog circuit and terminals of the logic circuit, outputting the result of comparing the function value generated by the function and an expected value, and, based on a result of the comparison, determining whether or not there is a connection error between the terminals of the analog circuit and the terminals of the logic circuit.


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Watanabe, Hitoshi. (2008). Semiconductor-circuit-device verifying method and cad apparatus for implementing the same (U.S. Patent No. 7420489). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7420489

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