The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
Jun. 08, 2006
Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces
Sabih Sabih, Austin, TX (US);
Jari Vahe, Austin, TX (US);
Sabih Sabih, Austin, TX (US);
Jari Vahe, Austin, TX (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2level testing, where the 1level testing is more stringent than the 2level testing. The testing continues by testing, at the 2level, remaining ones of the plurality of high-speed interfaces.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile