The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Jan. 04, 2006
Arthur Tung-tak Leung, Saratoga, CA (US);
Anthony LI, Los Altos, CA (US);
William Lynch, La Honda, CA (US);
Sharad Mehrotra, Saratoga, CA (US);
Arthur Tung-Tak Leung, Saratoga, CA (US);
Anthony Li, Los Altos, CA (US);
William Lynch, La Honda, CA (US);
Sharad Mehrotra, Saratoga, CA (US);
Cisco Technology, Inc., San Jose, CA (US);
Abstract
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.