Column decoder of semiconductor memory device, and method of generating column selection line signal in semiconductor memory device

Abstract

A column decoder of a semiconductor memory device includes an internal address output circuit, an address decoder, and a control circuit. The internal address output circuit converts an external column address into an internal column address and outputs the internal column address. The address decoder decodes a pre-decoded column address, which is obtained by decoding the internal column address, in response to a write column enable signal or in response to a read column enable signal activated earlier than the write column enable signal, and generates a column selection line signal for activating a memory cell designated by the external column address. The control circuit outputs a write signal or a read signal for controlling an output time of the internal column address. The address decoder generates a valid column selection line signal in response to a write signal in the write operation, and generates a valid column selection line signal in response to the read signal in a read operation.