Semiconductor memory device

Abstract

A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.