The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Nov. 03, 2006
Kazuya Yamamoto, Tokyo, JP;
Tomoyuki Asada, Tokyo, JP;
Hiroyuki Otsuka, Hyogo, JP;
Kosei Maemura, Tokyo, JP;
Kazuya Yamamoto, Tokyo, JP;
Tomoyuki Asada, Tokyo, JP;
Hiroyuki Otsuka, Hyogo, JP;
Kosei Maemura, Tokyo, JP;
Mitsubishi Electric Corporation, Tokyo, JP;
Abstract
A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.