Low-swing interconnections for field programmable gate arrays

Abstract

An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.