The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Jul. 05, 2005
Kyoung-woo Lee, Seoul, KR;
Hong-jae Shin, Seoul, KR;
Jeong-hoon Ahn, Gwacheon-si, KR;
Seung-man Choi, Gyeonggi-do, KR;
Byung-jun OH, Suwon-si, KR;
Yoon-hae Kim, Sungnam-si, KR;
Kyoung-Woo Lee, Seoul, KR;
Hong-Jae Shin, Seoul, KR;
Jeong-Hoon Ahn, Gwacheon-si, KR;
Seung-Man Choi, Gyeonggi-do, KR;
Byung-Jun Oh, Suwon-si, KR;
Yoon-Hae Kim, Sungnam-si, KR;
Abstract
In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.