The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2008

Filed:

Nov. 02, 2005
Applicants:

Sung-pil Jang, Yongin-si, KR;

Han-gu Kim, Seongnam-si, KR;

Chan-hee Jeon, Suwon-si, KR;

Inventors:

Sung-Pil Jang, Yongin-si, KR;

Han-Gu Kim, Seongnam-si, KR;

Chan-Hee Jeon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.


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