The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Feb. 19, 2007
Ramachandran Muralidhar, Austin, TX (US);
Rajesh A. Rao, Austin, TX (US);
Matthew T. Herrick, Cedar Park, TX (US);
Narayanan C. Ramani, Austin, TX (US);
Robert F. Steimle, Austin, TX (US);
Ramachandran Muralidhar, Austin, TX (US);
Rajesh A. Rao, Austin, TX (US);
Matthew T. Herrick, Cedar Park, TX (US);
Narayanan C. Ramani, Austin, TX (US);
Robert F. Steimle, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.