The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2008

Filed:

Dec. 12, 2003
Applicants:

Hajime Washio, Sakurai, JP;

Kazuhiro Maeda, Nara, JP;

Mamoru Onda, Tenri, JP;

Inventors:

Hajime Washio, Sakurai, JP;

Kazuhiro Maeda, Nara, JP;

Mamoru Onda, Tenri, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/00 (2006.01); G06F 3/038 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCKand SCKare supplied to the first data signal line driving circuit SD, while the first clock signal SCKis also supplied to the second data signal line driving circuit SDin parallel. The wiringsandfor the respective signals are adjusted to have equal wiring load with a dummy wiringprovided in the wiring, for solving uneven wiring load caused by difference of leading manner, the dummy wiringconstituting an additional capacitor section, together with a liquid crystal layer and a counter electrode.


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