The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2008

Filed:

Jun. 18, 2005
Applicants:

Yung-cheng MA, Hsinchu, TW;

Tengh-yih Wang, Shanhua Township, Tainan County, TW;

Hsien-feng Kuo, Taipei, TW;

Chi-lung Wang, Hsinchu, TW;

Inventors:

Yung-Cheng Ma, Hsinchu, TW;

Tengh-Yih Wang, Shanhua Township, Tainan County, TW;

Hsien-Feng Kuo, Taipei, TW;

Chi-Lung Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.


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