The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
Apr. 28, 2006
Håkan E. Zeffer, Uppsala, SE;
Erik E. Hagersten, Palo Alto, CA (US);
Anders Landin, San Carlos, CA (US);
Shailender Chaudhry, San Francisco, CA (US);
Paul N. Loewenstein, Palo Alto, CA (US);
Robert E. Cypher, Saratoga, CA (US);
Zoran Radovic, Lidingo, SE;
Håkan E. Zeffer, Uppsala, SE;
Erik E. Hagersten, Palo Alto, CA (US);
Anders Landin, San Carlos, CA (US);
Shailender Chaudhry, San Francisco, CA (US);
Paul N. Loewenstein, Palo Alto, CA (US);
Robert E. Cypher, Saratoga, CA (US);
Zoran Radovic, Lidingo, SE;
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.