The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7411416 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 12, 2008

Filed:

Apr. 29, 2005
Applicants:

Hideyuki Iida, Kawasaki, JP;

Yoshiro Tanaka, Kawasaki, JP;

Keisuke Nakamura, Kawasaki, JP;

Yosuke Konaka, Kawasaki, JP;

Takayuki Niiyama, Kawasaki, JP;

Daisuke Seki, Kawasaki, JP;

Inventors:

Hideyuki Iida, Kawasaki, JP;

Yoshiro Tanaka, Kawasaki, JP;

Keisuke Nakamura, Kawasaki, JP;

Yosuke Konaka, Kawasaki, JP;

Takayuki Niiyama, Kawasaki, JP;

Daisuke Seki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a Thevenin termination circuit that is arranged on the data bus at a point. The Thevenin termination circuit maintains a voltage at the point substantially equal to the first voltage.


Find Patent Forward Citations

Iida, Hideyuki. (2008). Technology for supressing noise of data bus circuit (U.S. Patent No. 7411416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7411416

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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