The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
Jul. 05, 2006
Hun-hyeoung Leam, Yongin-si, KR;
Hyeon-deok Lee, Seoul, KR;
Young-sub You, Pyeongtaek-si, KR;
Won-jun Jang, Seoul, KR;
Woong Lee, Seoul, KR;
Jung-hyun Park, Seoul, KR;
Sang-kyoung Lee, Incheon, KR;
Jung-geun Jee, Seongnam-si, KR;
Sang-hoon Lee, Seoul, KR;
Hun-Hyeoung Leam, Yongin-si, KR;
Hyeon-Deok Lee, Seoul, KR;
Young-Sub You, Pyeongtaek-si, KR;
Won-Jun Jang, Seoul, KR;
Woong Lee, Seoul, KR;
Jung-Hyun Park, Seoul, KR;
Sang-Kyoung Lee, Incheon, KR;
Jung-Geun Jee, Seongnam-si, KR;
Sang-Hoon Lee, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.