The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2008

Filed:

Dec. 15, 2005
Applicants:

Jason Pritchard, Hopkinton, MA (US);

Venkat Raghavan Satagopan, Rolla, MO (US);

Inventors:

Jason Pritchard, Hopkinton, MA (US);

Venkat Raghavan Satagopan, Rolla, MO (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a user. The set of global circuit board dimension parameters defines a set of global circuit board dimensions of the circuit board structure. The technique further includes forming, for each layer, a set of individual circuit board dimension parameters defining a set of individual circuit board dimensions for that layer based on the set of global circuit board dimension parameters. The technique further includes providing a script for use by a 3D modeling subsystem. The script includes a set of circuit board design values based on the set of individual circuit board dimension parameters formed for each layer. Other properties such as layer width and thickness, via dimensions, etc. are handled in a similar manner.


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