Asynchronous communication among hardware object nodes in ic with receive and send ports protocol registers using temporary register bypass select for validity information

Abstract

Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending port, each structured to send messages along communication pathways, which are connected between a sending and a receiving port. Individual communication pathways may operate at different clock frequencies from one another and messages sent along them may be asynchronous from one node to another. Sending ports are structured to stall until the sending port receives notice that the receiving port is able to accept a message. Additionally, sending ports include protocol information that eliminates the necessity for message timing oversight, and instead, the delivery of each message is made on the local level independent of the operating speed of the port's attached processor or of the communication network itself. Messages may be sent across clock boundaries without data loss.