On-chip esd protection circuit for compound semiconductor heterojunction bipolar transistor rf circuits

Abstract

A low loading capacitance on-chip electrostatic discharge (ESD) protection circuit for compound semiconductor power amplifiers is disclosed, which does not degrade the circuit RF performance. Its principle of operation and simulation results regarding capacitance loading, leakage current, degradation to RF performance are disclosed. The design, loading effect over frequency, robustness over process and temperature variation and application to an RF power amplifier is presented in detail. The ESD circuit couples an input to ground during ESD surges through a diode string coupled to the input, and a transistor switch or Darlington pair having its gate coupled to and triggered by the diode string. The Darlington pair couples the input to ground when triggered through a low impedance path in parallel to the diode string. A reverse diode also couples ground to the input on reverse surges.