The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2008

Filed:

Mar. 23, 2005
Applicants:

Ji-hoon Park, Seoul, KR;

Sung-taeg Kang, Seoul, KR;

Seong-gyun Kim, Seongnam-si, KR;

Bo-young Seo, Anyang-si, KR;

Sung-woo Park, Gunpo-si, KR;

Inventors:

Ji-Hoon Park, Seoul, KR;

Sung-Taeg Kang, Seoul, KR;

Seong-Gyun Kim, Seongnam-si, KR;

Bo-Young Seo, Anyang-si, KR;

Sung-Woo Park, Gunpo-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.


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