The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2008

Filed:

Apr. 06, 2005
Applicants:

Tea-kwang Yu, Suwon-si, KR;

Weon-ho Park, Suwon-si, KR;

Kyoung-hwan Kim, Hwaseong-si, KR;

Kwang-tae Kim, Suwon-si, KR;

Inventors:

Tea-kwang Yu, Suwon-si, KR;

Weon-ho Park, Suwon-si, KR;

Kyoung-hwan Kim, Hwaseong-si, KR;

Kwang-tae Kim, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.


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