The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2008
Filed:
Mar. 29, 2005
Ramesh Venugopal, Richardson, TX (US);
Christoph Wasshuber, Parker, TX (US);
David Barry Scott, Plano, TX (US);
Ramesh Venugopal, Richardson, TX (US);
Christoph Wasshuber, Parker, TX (US);
David Barry Scott, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region () is formed within a semiconductor body (). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (). A high-k dielectric layer () is formed over the device (). A polysilicon layer () is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer () and the polysilicon layer () are patterned to form polysilicon gate structures. P-type source/drain regions () are formed within the n-type well region ().