The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2008
Filed:
Oct. 03, 2005
Ker Yon Lau, Penang, MY;
Ker Yon Lau, Penang, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Techniques are provided for capturing external signals at output pins on a programmable logic integrated circuit (IC) during a boundary scan test. A JTAG sample signal is routed to an input/output block on a chip and active during a JTAG sampling phase. An input buffer coupled to an output pin is turned on during the JTAG sample phase. Logic gates enable the input buffer in response to the JTAG sample signal so that the input buffer can capture a signal on the pin. The input buffer is turned off after the JTAG sampling phase to conserve power. The output buffer coupled to the pin that receives the test signal is tristated to prevent contention during the JTAG sampling phase. The techniques of the present invention can be used to test board level interconnects in less time and are easy to implement.