Ic comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability

Abstract

Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual communication channels operate at individually controllable clock speeds. Data messages sent between nodes pass at the speed of the communication channels. These data messages are sent by a sending port that includes registers for storing data and registers for protocol signals that control the timing and movement of the data. Data crosses clock boundaries without data loss. At least some of the microprocessors include fork functions that output a data stream to more than one output port. Similarly, at least some of the microprocessors include join functions that can create a single data stream from inputs from more than one input port.